Efficient implementation of serial search synchronization sub-system for direct sequence spread spectrum system using FPGA

الملخص EN

A complete synchronization / detection sub-system for direct sequence spread spectrum (DS / SS) system has been designed and implemented using Xilinx-Virtex Field Programmable Gate Array (FPGA) device.

Then, a number of modifications have been made to the original sub-system to obtain optimum FPGA cost / delay optimization.

For this purpose, the 8 bit representation of BPSK DS / SS-signal was replaced by only one bit representation with the same performance at middle values of signal-to-noise ratio.

The synthesis and implementation reports of VHDL programs that written to model both systems are developed for comparison purpose.

These reports show that the modified implementation offers a cost reduction factor of 95.8 % and delay reduction factor of50 % as compared with the traditional one.