Modules for Pipelined Mixed Radix FFT Processors

Abstract EN

A set of soft IP cores for the Winograd r -point fast Fourier transform (FFT) is considered.

The cores are designed by the method of spatial SDF mapping into the hardware, which provides the minimized hardware volume at the cost of slowdown of the algorithm by r times.

Their clock frequency is equal to the data sampling frequency.

The cores are intended for the high-speed pipelined FFT processors, which are implemented in FPGA.