Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design
Joint Authors
Tiwari, Sudarshan
Nagaria, Rajendra Kumar
Wairya, Subodh
Source
Issue
Vol. 2012, Issue 2012 (31 Dec. 2012), pp.1-18, 18 p.
Publisher
Hindawi Publishing Corporation
Publication Date
2012-04-04
Country of Publication
Egypt
No. of Pages
18
Main Subjects
Engineering Sciences and Information Technology
Abstract EN
This paper presents a comparative study of high-speed and low-voltage full adder circuits.
Our approach is based on hybrid design full adder circuits combined in a single unit.
A high performance adder cell using an XOR-XNOR (3T) design style is discussed.
This paper also discusses a high-speed conventional full adder design combined with MOSCAP Majority function circuit in one unit to implement a hybrid full adder circuit.
Moreover, it presents low-power Majority-function-based 1-bit full addersthat use MOS capacitors (MOSCAP) in its structure.
This technique helps in reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design.
Simulation results illustrate the superiority of the designed adder circuits over the conventional CMOS, TG, and hybrid adder circuits in terms of power, delay, power delay product (PDP), and energy delay product (EDP).
Postlayout simulation results illustrate the superiority of the newly designed majority adder circuits against the reported conventional adder circuits.
The design is implemented on UMC 0.18 μm process models in Cadence Virtuoso Schematic Composer at 1.8 V single-ended supply voltage, and simulations are carried out on Spectre S.
American Psychological Association (APA)
Wairya, Subodh& Nagaria, Rajendra Kumar& Tiwari, Sudarshan. 2012. Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design. VLSI Design،Vol. 2012, no. 2012, pp.1-18.
https://search.emarefa.net/detail/BIM-451714
Modern Language Association (MLA)
Wairya, Subodh…[et al.]. Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design. VLSI Design No. 2012 (2012), pp.1-18.
https://search.emarefa.net/detail/BIM-451714
American Medical Association (AMA)
Wairya, Subodh& Nagaria, Rajendra Kumar& Tiwari, Sudarshan. Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design. VLSI Design. 2012. Vol. 2012, no. 2012, pp.1-18.
https://search.emarefa.net/detail/BIM-451714
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-451714