One Clock-Cycle Response 0.5 μm CMOS Dual-Mode ΣΔ DC-DC Bypass Boost Converter Stable over Wide RESRLC Variations

Abstract EN

Power supplies in portable applications must not only conform and adapt to their highly integrated on-chip and in-package environments but also, more intrinsically, respond quickly to fast load dumps to achieve and maintain high accuracy.

The frequency-compensation network, however, limits speed and regulation performance because it must cater to all combinations of filter capacitor CO, inductor L, and CO's equivalent series resistance RESR resulting from tolerance and modal design targets.

As such, it must compensate the worst-case condition and therefore restrain the performance of all other possible scenarios, even if the likelihood of occurrence of the latter is considerably high and the former substantially low.

Sigma-delta (ΣΔ) control, which addresses this issue in buck converters by easing its compensation requirements and offering one-cycle transient response, has not been able to simultaneously achieve high bandwidth, high accuracy, and wide RESRLC compliance in boost converters.

This paper presents a dual-mode ΣΔ boost bypass converter, which by using a high-bandwidth bypass path only during transient load-dump events was experimentally 1.41 to 6 times faster than the state of the art in current-mode ΣΔ boost supplies, and this without any compromise in RESRLC compliance range (0–50 mΩ, 1–30 μH, and 1–350 μF).