Optimizing the performance of MOS stacks

Author

Sharrush, Sharif M.

Source

The Iraqi Journal of Electrical and Electronic Engineering

Issue

Vol. 16, Issue 1 (30 Jun. 2020), pp.85-98, 14 p.

Publisher

University of Basrah College of Engineering

Publication Date

2020-06-30

Country of Publication

Iraq

No. of Pages

14

Main Subjects

Electronic engineering

Topics

Abstract EN

CMOS stack circuits find applications in multi-input exclusive-OR gates and barrel-shifters.

Specifically, in wide fan-in CMOS NAND/NOR gates, the need arises to connect a relatively large number of NMOS/PMOS transistors in series in the pull-down network (PDN)/pull-up network (PUN).

The resulting time delay is relatively high and the power consumption accordingly increases due to the need to deal with the various internal capacitances.

The problem gets worse with increasing the number of inputs.

In this paper, the performance of conventional static CMOS stack circuits is investigated quantitatively and a figure of merit expressing the performance is defined.

The word “performance” includes the following three metrics; the average propagation delay, the power consumption, and the area.

The optimum scaling factor corresponding to the best performance is determined.

It is found that under the worst-case low-to-high transition at the output (that is, the input combination that results in the longest time delay in case of logic “1” at the output), there is an optimum value for the sizing of the PDN in order to minimize the average propagation delay.

The proposed figure of merit is evaluated for different cases with the results discussed.

The adopted models and the drawn conclusions are verified by comparison with simulation results adopting the 45 nm CMOS technology.

American Psychological Association (APA)

Sharrush, Sharif M.. 2020. Optimizing the performance of MOS stacks. The Iraqi Journal of Electrical and Electronic Engineering،Vol. 16, no. 1, pp.85-98.
https://search.emarefa.net/detail/BIM-972155

Modern Language Association (MLA)

Sharrush, Sharif M.. Optimizing the performance of MOS stacks. The Iraqi Journal of Electrical and Electronic Engineering Vol. 16, no. 1 (Jun. 2020), pp.85-98.
https://search.emarefa.net/detail/BIM-972155

American Medical Association (AMA)

Sharrush, Sharif M.. Optimizing the performance of MOS stacks. The Iraqi Journal of Electrical and Electronic Engineering. 2020. Vol. 16, no. 1, pp.85-98.
https://search.emarefa.net/detail/BIM-972155

Data Type

Journal Articles

Language

English

Notes

Includes bibliographical references : p. 97-98

Record ID

BIM-972155