Design and Implementation of Cache Memory with Dual Unit TileLine Accessibility
المؤلف
المصدر
Mathematical Problems in Engineering
العدد
المجلد 2019، العدد 2019 (31 ديسمبر/كانون الأول 2019)، ص ص. 1-12، 12ص.
الناشر
Hindawi Publishing Corporation
تاريخ النشر
2019-04-01
دولة النشر
مصر
عدد الصفحات
12
التخصصات الرئيسية
الملخص EN
In recent years, the increasing disparity between the data access speed of cache and processing speeds of processors has caused a major bottleneck in achieving high-performance 2-dimensional (2D) data processing, such as that in scientific computing and image processing.
To solve this problem, this paper proposes new dual unit tile/line access cache memory based on a hierarchical hybrid Z-ordering data layout and multibank cache organization supporting skewed storage schemes.
The proposed layout improves 2D data locality and reduces L1 cache misses and Translation Lookaside Buffer (TLB) misses efficiently and it is transformed from conventional raster layout by a simple hardware-based address translation unit.
In addition, we proposed an aligned tile set replacement algorithm (ATSRA) for reduction of the hardware overhead in the tag memory of the proposed cache.
Simulation results using Matrix Multiplication (MM) illustrated that the proposed cache with parallel unit tile/line accessibility can reduce both the L1 cache and TLB misses considerably as compared with conventional raster layout and Z-Morton order layout.
The number of parallel load instructions for parallel unit tile/line access was reduced to only about one-fourth of the conventional load instruction.
The execution time for parallel load instruction was reduced to about one-third of that required for conventional load instruction.
By using 40 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology, we combined the proposed cache with a SIMD-based data path and designed a 5 × 5 mm2 Large-Scale Integration (LSI) chip.
The entire hardware overhead of the proposed ATSRA-cache was reduced to only 105% of that required for a conventional cache by using the ATSRA method.
نمط استشهاد جمعية علماء النفس الأمريكية (APA)
Wang, Baokang. 2019. Design and Implementation of Cache Memory with Dual Unit TileLine Accessibility. Mathematical Problems in Engineering،Vol. 2019, no. 2019, pp.1-12.
https://search.emarefa.net/detail/BIM-1200709
نمط استشهاد الجمعية الأمريكية للغات الحديثة (MLA)
Wang, Baokang. Design and Implementation of Cache Memory with Dual Unit TileLine Accessibility. Mathematical Problems in Engineering No. 2019 (2019), pp.1-12.
https://search.emarefa.net/detail/BIM-1200709
نمط استشهاد الجمعية الطبية الأمريكية (AMA)
Wang, Baokang. Design and Implementation of Cache Memory with Dual Unit TileLine Accessibility. Mathematical Problems in Engineering. 2019. Vol. 2019, no. 2019, pp.1-12.
https://search.emarefa.net/detail/BIM-1200709
نوع البيانات
مقالات
لغة النص
الإنجليزية
الملاحظات
Includes bibliographical references
رقم السجل
BIM-1200709
قاعدة معامل التأثير والاستشهادات المرجعية العربي "ارسيف Arcif"
أضخم قاعدة بيانات عربية للاستشهادات المرجعية للمجلات العلمية المحكمة الصادرة في العالم العربي
تقوم هذه الخدمة بالتحقق من التشابه أو الانتحال في الأبحاث والمقالات العلمية والأطروحات الجامعية والكتب والأبحاث باللغة العربية، وتحديد درجة التشابه أو أصالة الأعمال البحثية وحماية ملكيتها الفكرية. تعرف اكثر