A hardware-efficient block matching unit for H. 265-HEVC motion estimation engine using bit-shrinking

الملخص EN

The main objective of this work is to enhance the processing performance of the recently introduced video codec H.

265/HEVC.

Since most of the computations of H.

265/HEVC still occur in the motion estimation engine which is inherited from its predecessor H.264/AVC, we propose a bit-shrinking approach with a modified logic functionality to design an efficient and simplified block matching unit that replaces the already used Sum of Absolute Differences (SAD) unit.

The hardware complexity of the proposed unit itself is reduced and the number of its generated output bits is reduced as well which in turn simplifies all the subsequent units of motion estimation.

The hardware complexity, the consumed power and the processing delay of the motion estimation engine are therefore reduced significantly with only marginal deterioration in both the bit-rate and the peak-signal-to-noise-ratios (PSNR) of the tested High Definition (HD) and Ultra-High Definition (UHD) H.265/HEVC compressed videos.

We simulate our design using HM16.6 and perform system logic synthesis using Synopsys’s Design Compiler, targeting ASIC, for evaluation purposes.