Low latency, high throughput, and less complex VLSI architecture for 2D-DFT

الملخص EN

This paper proposes a pipelined, systolic architecture for two-dimensional discrete Fourier transform computation which is highly concurrent.

The architecture consists of two, one-dimensional discrete Fourier transform blocks connected via an intermediate buffer.

The proposed architecture offers low latency as well as high throughput and can perform both oneand two-dimensional discrete Fourier transforms.

The architecture supports transform length that is not power of two and not based on products of co-prime numbers.

The simulation and synthesis were carried out using Cadence tools, NcSim and RTL Compiler, respectively, with 180 nm libraries.