Arithmetic and logic unit design using VHDL language

الملخص EN

This paper deals with designing a model for the Arithmetic and Logic Unit (ALU), which can be said as the basic building block of the Central Processing Unit (CPU) in a computer.

A model of the ALU has been designed to perform a set of operations, which includes both arithmetic and logical operations, using the Very High Speed Integrated Circuit Hardware Description Language (VHDL), due to its wide spread and high level of accuracy in the world of digital design.

Each hardware component has been designed and tested individually to ensure its functionality, and thus to ensure the functionality of the ALU as a single unit, before its real implementation.

The results prove that each component correctly performs all the operations required of it, whether it is alone or within the ALU component