Computer-based training (CBT)‎ for dependable simulation of digital circuits fault detection using digital signature

الملخص EN

This paper adopts the concept of computer-based training (CBT) and digital signature in training labs for fault detection of digital circuits.

An algorithm is used for fault detection and back tracing for fault location using signature node-pattern in the digital circuits under test (CUT).

A vector of bits is developed as a third party for test-signature measurements.

A message is popped up to highlight the fault and the location of the defected nodes.

Bit pattern at inputs as well as that at output of the unit under test (UUT) are stored as templates (reference vectors) for later matching measurements.

A comparator is assigned for the matching between the group of the test nodes and the reference vector.

The proposed algorithm intended to substitute the static nature and narrow area in real-time measurement in digital circuits and provides the property of dependability.In the proposed algorithm, if output is OK then there is no faulty nodes, otherwise backward nodes are traced and matching measurement is carried out to detect the reason for malfunction of the UUT.

A well known general testing of digital circuit using signature matching (SM) is a technique that can be used to detect an error in data stream caused by hardware faults.

A brief description of the adopted mechanism of SM to be used applying CBT is described.

The paper considers the basic paradigms in this field in real time as well as workbench package to design a digital circuit.

Fault detection and CBT technology emphasizes the cost effectiveness of E-learning in various learning systems environments.

Digital circuits are simulated and broadcasted.

Four groups design different faulty virtual circuits in different nodes.

Tracing and testing are successfully performed with reasonable results.

It is important to point at the significant capability of open sourcing that enables the trainees to modify the algorithm according to the digital circuit requirements (number of UUT and consequently the number of nodes).

It is only needed to modify the dimension of the matrix of reference signature of the pointed UUT.

The proposed algorithm simply, finds out the defected node directly from XOR output.

Four different digital circuits are put under test to verify the algorithm.

The pseudo-code describing the proposed algorithm is illustrated.

The proposed algorithm simulate the real time trouble shooting of digital circuits.

It suggests a fault the perform a matching measurement between test and reference signatures of nodes.

It is promising for virtual digital circuit labs.

The underling objective is to reduce the number of the electronic laboratories.

The fault detection algorithm provides simplicity, minimum execution test time, accuracy and universal testing.

All these aspects signify the value of the E-learning methodologies with the proposed algorithm