An FPGA based adaptive noise canceller using adjusted step size LMS algorithm with enhanced performance

مقدم أطروحة جامعية

Muhammad, Haydar Abd al-Latif

مشرف أطروحة جامعية

Jamil, Thamir Muhammad

الجامعة

الجامعة التكنولوجية

الكلية

-

القسم الأكاديمي

قسم الهندسة الكهروميكانيكية

دولة الجامعة

العراق

الدرجة العلمية

ماجستير

تاريخ الدرجة العلمية

2011

الملخص الإنجليزي

-This thesis searches on how to improve the performance of ANC using variable step size algorithm and the implementation of ANC on FPGA.

In this thesis, an Absolute Average Errorbased Adjusted Step Size LMS (AAE-ASSLMS) algorithm is proposed, which overcomes and avoids one of the drawbacks of the standard LMS algorithm.

This drawback is convergence speed – misadjustment tradeoff problem.

In this algorithm an appropriate time varying value of the step size is calculated based on gradually decreasing maximum step size to the minimum value.

This time varying step size is based on the absolute average value of the current and the previous estimation errors.

A comparison of LMS, proposed, and another VSSLMS adaptive algorithms is carried out.

An adaptive noise canceller was built and training using MATLAB simulation program as a form of software to test the right operation of adaptive noise canceller.

For time variant reference input, results indicated that (AAE-ASSLMS) has a difference value approximately (0.5917, 0.1754) in the level of misadjustment when the filter length equals (8) compared with VSSLMS and LMS algorithms respectively.

In addition, the proposed algorithm verifies (16, 13) dB difference in attenuation factor compared with other algorithms.

Moreover, for SNR equals (-20) dB the proposed algorithm records (0.7044, 0.0593) difference in misadjustment and (17, 12) dB difference in attenuation factor compared with VSSLMS and LMS algorithms respectively.

Simulation results show that the Adaptive FIR filter (AFIR) coefficients of ANC using AAE-ASSLMS converges fast to the noise path coefficients and has good estimation coefficients than the other algorithms.

All simulation results showed that the AAE-ASSLMS algorithm is more suitable in implementing the adaptive filter in field programmable gate array (FPGA).

However, adaptive filtering algorithms assume infinite-precision, whereas in reality digital hardware is of finiteprecision.

So, this produces a lot of problems such as staling, slow down, saturation and over word length bits.

The effects of finite-precision on adaptive algorithms are studied in detail and techniques for reducing these effects are presented.

Each component of the system design is built using VHLD language and then it is translated to the schematic library of Xilinx ISE 10.1i for use in complete system design, except the multiplier is built using embedded multiplier.

A new proposed method that aims to make a connection between MATLAB and Xilinx ISE is used.

This connection is made in order to overcome the problem of delivering a speech signal to Xilinx ISE 10.1i.

Simulation results show that the difference between the error signal that is obtained by Xilinx ISE simulator and MATLAB simulation is very small (i.e.

quantization error is very small).

التخصصات الرئيسية

تكنولوجيا المعلومات وعلم الحاسوب

• APA
• MLA
• AMA

لغة النص

الإنجليزية

نوع البيانات

رسائل جامعية

رقم السجل

BIM-305061