Design and implementation of CDMA2000 processor based on SDR using FPGA

مقدم أطروحة جامعية

Isa, Ala Yusuf

مشرف أطروحة جامعية

Zibun, Hadi T.

الجامعة

الجامعة التكنولوجية

الكلية

-

القسم الأكاديمي

قسم الهندسة الكهربائية

دولة الجامعة

العراق

الدرجة العلمية

ماجستير

تاريخ الدرجة العلمية

2011

الملخص الإنجليزي

-The aim of this thesis is to investigate the possibility of using 32QAM and 64QAM in order to increase the data rate firstly.

It also aims at investigating the possibility of using Simulink HDL coder in implementation to get the flexibility in the design and reduce the time of implementation.

However, works related to the implementation of CDMA2000 with Simulink HDL coder and using 32QAM and 64QAM have not been reported before.

The performance simulated of forward link channel of CDMA2000 system was established in the presence of noise and fading by using MATLAB.

All programs of this simulation are represented in the object oriented programing and by using m-file.

The results show that the forward link channel of CDMA2000 with 32QAM and 64QAM is a suitable technique to increase the data rate up to 2Mbps in the presence of noise and fading.

Results of simulation for forward link channel of CDMA2000 system in the present of noise shows improvement when using three levels of codes (LPNC, Walsh code and complex coding) for QPSK modulation the system performance is improved from (1.8 to 1.9) E?⁄NO in dB with Bit Error Rate (BER) 10?? to 10?? and for 8QAM the system performance is improved at (2.9) E?⁄NO in dB within BER 10?? to 10?? and for 16QAM the system performance is improved from (1.2 to 1) E?⁄NO in dB within BER 10?? to 10?? and for 32QAM the system performance is improved from (2.8 to 2.9) E?⁄NO in dB within BER 10?? to 10?? and for 64QAM the system performance is improved from (3 to 3.2) E?⁄NO in dB within BER 10?? to 10??.

As well as the result of simulation in the present of noise and fading improvement with 0.5 E?⁄NO in dB for different Doppler Frequencies (5,45,90,160,230) Hz.

The Simulink HDL Coder has been used for converting the MATLAB-Simulink models to VHDL language.

The verification of the generated VHDL code has been done using Altera- ModelSim, while the synthesis reports and board programming files have been obtained using the Quartus II.

System implementation has been done using FPGA technology with Altera Cyclone II boards.

The implementation of the forward link channel by using Simulink HDL coder shows feasibility and flexibility in solving the problem of complex multiplication of complex spreading code also the practical results were closed to that obtained from ModelSim.

التخصصات الرئيسية

هندسة الاتصالات

• APA
• MLA
• AMA

لغة النص

الإنجليزية

نوع البيانات

رسائل جامعية

رقم السجل

BIM-305318