RTL structural synthesis from behavioral descriptions in a UNIX environment

الملخص EN

High level synthesis refers to the process of synthesizing the hardware of a digital system from a high level description.

This paper presents an integrated system which accepts as input a purely behavioral description expressed in the “be” language and transforms it into hardware (IC layout).

The be description is first transformed into a stack representation which is used to generate an optimized RTL description in the AHPL language.

The AHPL description is finally synthesized into hardware.