High-Level Synthesis of In-Circuit Assertions for Verification, Debugging, and Timing Analysis
المؤلفون المشاركون
George, Alan D.
Curreri, John
Stitt, Greg
المصدر
International Journal of Reconfigurable Computing
العدد
المجلد 2011، العدد 2011 (31 ديسمبر/كانون الأول 2011)، ص ص. 1-17، 17ص.
الناشر
Hindawi Publishing Corporation
تاريخ النشر
2011-01-12
دولة النشر
مصر
عدد الصفحات
17
التخصصات الرئيسية
تكنولوجيا المعلومات وعلم الحاسوب
الملخص EN
Despite significant performance and power advantages compared to microprocessors, widespread usage of FPGAs has been limited by increased design complexity.
High-level synthesis (HLS) tools have reduced design complexity but provide limited support for verification, debugging, and timing analysis.
Such tools generally rely on inaccurate software simulation or lengthy register-transfer-level simulations, which are unattractive to software developers.
In this paper, we introduce HLS techniques that allow application designers to efficiently synthesize commonly used ANSI-C assertions into FPGA circuits, enabling verification and debugging of circuits generated from HLS tools, while executing in the actual FPGA environment.
To verify that HLS-generated circuits meet execution timing constraints, we extend the in-circuit assertion support for testing of elapsed time for arbitrary regions of code.
Furthermore, we generalize timing assertions to transparently provide hang detection that back annotates hang occurrences to source code.
The presented techniques enable software developers to rapidly verify, debug, and analyze timing for FPGA applications, while reducing frequency by less than 3% and increasing FPGA resource utilization by 0.7% or less for several application case studies on the Altera Stratix-II EP2S180 and Stratix-III EP3SE260 using Impulse-C.
The presented techniques reduced area overhead by as much as 3x and improved assertion performance by as much as 100% compared to unoptimized in-circuit assertions.
نمط استشهاد جمعية علماء النفس الأمريكية (APA)
Curreri, John& Stitt, Greg& George, Alan D.. 2011. High-Level Synthesis of In-Circuit Assertions for Verification, Debugging, and Timing Analysis. International Journal of Reconfigurable Computing،Vol. 2011, no. 2011, pp.1-17.
https://search.emarefa.net/detail/BIM-469625
نمط استشهاد الجمعية الأمريكية للغات الحديثة (MLA)
Curreri, John…[et al.]. High-Level Synthesis of In-Circuit Assertions for Verification, Debugging, and Timing Analysis. International Journal of Reconfigurable Computing No. 2011 (2011), pp.1-17.
https://search.emarefa.net/detail/BIM-469625
نمط استشهاد الجمعية الطبية الأمريكية (AMA)
Curreri, John& Stitt, Greg& George, Alan D.. High-Level Synthesis of In-Circuit Assertions for Verification, Debugging, and Timing Analysis. International Journal of Reconfigurable Computing. 2011. Vol. 2011, no. 2011, pp.1-17.
https://search.emarefa.net/detail/BIM-469625
نوع البيانات
مقالات
لغة النص
الإنجليزية
الملاحظات
Includes bibliographical references
رقم السجل
BIM-469625
قاعدة معامل التأثير والاستشهادات المرجعية العربي "ارسيف Arcif"
أضخم قاعدة بيانات عربية للاستشهادات المرجعية للمجلات العلمية المحكمة الصادرة في العالم العربي
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