An Inductorless Cascaded Phase-Locked Loop with Pulse Injection Locking Technique in 90 nm CMOS

الملخص EN

An inductorless phase-locked loop with subharmonic pulse injection locking was realized (PLL area: 0.11 mm2) by adopting 90 nm Si CMOS technology.

The proposed circuit is configured with two cascaded PLLs; one of them is a reference PLL that generates reference signals to the other one from low-frequency external reference signals.

The other is a main PLL that generates high-frequency output signals.

A high-frequency half-integral subharmonic locking technique was used to decrease the phase noise characteristics.

For a 50 MHz input reference signal, without injection locking, the 1 MHz offset phase noise was −88 dBc/Hz at a PLL output frequency of 7.2 GHz (= 144 × 50 MHz); with injection locking, the noise was −101 dBc/Hz (spur level: −31 dBc; power consumption from a 1.0 V power supply: 25 mW).