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High-Level Synthesis : Productivity, Performance, and Software Constraints
المؤلفون المشاركون
Min, Dongbo
Rupnow, Kyle
Liang, Yun
Li, Yinan
Chen, Deming
Do, Minh N.
المصدر
Journal of Electrical and Computer Engineering
العدد
المجلد 2012، العدد 2012 (31 ديسمبر/كانون الأول 2012)، ص ص. 1-14، 14ص.
الناشر
Hindawi Publishing Corporation
تاريخ النشر
2012-02-07
دولة النشر
مصر
عدد الصفحات
14
التخصصات الرئيسية
العلوم الهندسية و تكنولوجيا المعلومات
تكنولوجيا المعلومات وعلم الحاسوب
الملخص EN
FPGAs are an attractive platform for applications with high computation demand and low energy consumption requirements.
However, design effort for FPGA implementations remains high—often an order of magnitude larger than design effort using high-level languages.
Instead of this time-consuming process, high-level synthesis (HLS) tools generate hardware implementations from algorithm descriptions in languages such as C/C++ and SystemC.
Such tools reduce design effort: high-level descriptions are more compact and less error prone.
HLS tools promise hardware development abstracted from software designer knowledge of the implementation platform.
In this paper, we present an unbiased study of the performance, usability and productivity of HLS using AutoPilot (a state-of-the-art HLS tool).
In particular, we first evaluate AutoPilot using the popular embedded benchmark kernels.
Then, to evaluate the suitability of HLS on real-world applications, we perform a case study of stereo matching, an active area of computer vision research that uses techniques also common for image denoising, image retrieval, feature matching, and face recognition.
Based on our study, we provide insights on current limitations of mapping general-purpose software to hardware using HLS and some future directions for HLS tool development.
We also offer several guidelines for hardware-friendly software design.
For popular embedded benchmark kernels, the designs produced by HLS achieve 4X to 126X speedup over the software version.
The stereo matching algorithms achieve between 3.5X and 67.9X speedup over software (but still less than manual RTL design) with a fivefold reduction in design effort versus manual RTL design.
نمط استشهاد جمعية علماء النفس الأمريكية (APA)
Liang, Yun& Rupnow, Kyle& Li, Yinan& Min, Dongbo& Do, Minh N.& Chen, Deming. 2012. High-Level Synthesis : Productivity, Performance, and Software Constraints. Journal of Electrical and Computer Engineering،Vol. 2012, no. 2012, pp.1-14.
https://search.emarefa.net/detail/BIM-488083
نمط استشهاد الجمعية الأمريكية للغات الحديثة (MLA)
Liang, Yun…[et al.]. High-Level Synthesis : Productivity, Performance, and Software Constraints. Journal of Electrical and Computer Engineering No. 2012 (2012), pp.1-14.
https://search.emarefa.net/detail/BIM-488083
نمط استشهاد الجمعية الطبية الأمريكية (AMA)
Liang, Yun& Rupnow, Kyle& Li, Yinan& Min, Dongbo& Do, Minh N.& Chen, Deming. High-Level Synthesis : Productivity, Performance, and Software Constraints. Journal of Electrical and Computer Engineering. 2012. Vol. 2012, no. 2012, pp.1-14.
https://search.emarefa.net/detail/BIM-488083
نوع البيانات
مقالات
لغة النص
الإنجليزية
الملاحظات
Includes bibliographical references
رقم السجل
BIM-488083
قاعدة معامل التأثير والاستشهادات المرجعية العربي "ارسيف Arcif"
أضخم قاعدة بيانات عربية للاستشهادات المرجعية للمجلات العلمية المحكمة الصادرة في العالم العربي
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