FPGA Acceleration of Communication-Bound Streaming Applications : Architecture Modeling and a 3D Image Compositing Case Study

الملخص EN

Reconfigurable computers usually provide a limited number of different memory resources, such as host memory, external memory, and on-chip memory with different capacities and communication characteristics.

A key challenge for achieving high-performance with reconfigurable accelerators is the efficient utilization of the available memory resources.

A detailed knowledge of the memories' parameters is key for generating an optimized communication layout.

In this paper, we discuss a benchmarking environment for generating such a characterization.

The environment is built on IMORC, our architectural template and on-chip network for creating reconfigurable accelerators.

We provide a characterization of the memory resources available on the XtremeData XD1000 reconfigurable computer.

Based on this data, we present as a case study the implementation of a 3D image compositing accelerator that is able to double the frame rate of a parallel renderer.