A Heuristic Scheduler for Port-Constrained Floating-Point Pipelines

الملخص EN

We describe a heuristic scheduling approach for optimizing floating-point pipelines subject to input port constraints.

The objective of our technique is to maximize functional unit reuse while minimizing the following performance metrics in the generated circuit: (1) maximum multiplexer fanin, (2) datapath fanout, (3) number of multiplexers, and (4) number of registers.

For a set of systems biology markup language (SBML) benchmark expressions, we compare the resource usages given by our method to those given by a branch-and-bound enumeration of all valid schedules.

Compared with the enumeration results, our heuristic requires on average 33.4% less multiplexer bits and 32.9% less register bits than the worse case, while only requiring 14% more multiplexer bits and 4.5% more register bits than the optimal case.

We also compare our results against those given by the state-of-art high-level synthesis tool Xilinx AutoESL.

For the most complex of our benchmark expressions, our synthesis technique requires 20% less FPGA slices than AutoESL.