A D-type flip-flop with enhanced timing using CMOS technology and low supply voltage

العناوين الأخرى

قلاب التأخير الإلكتروني بتوقيت محسن باستخدام تكنلوجيا (CMOS)‎ و مزود طاقة منخفض الجهد

مقدم أطروحة جامعية

Bundug, Usamah Nasir

مشرف أطروحة جامعية

Abu Gharbiyah, Khaldun

أعضاء اللجنة

Shahruri, Fadi
Muhammad, Bassam
Mismar, Muhammad

الجامعة

جامعة الأميرة سمية للتكنولوجيا

الكلية

كلية الملك عبدالله الثاني للهندسة

القسم الأكاديمي

قسم الهندسة الكهربائية

دولة الجامعة

الأردن

الدرجة العلمية

ماجستير

تاريخ الدرجة العلمية

2017

الملخص الإنجليزي

First and foremost, praises and thanks to Allah almighty, for his many blessings which made me who I am today.

Allah has given me the power to believe in my passion and pursue my dreams.

I could never have done this thesis without the faith I have in Allah.

I am extremely grateful and thankful to my parents.

I can barely find the words to express all the wisdom, love and support you've given me.

I am very blessed to have such a parents like you in my life.

I would like to thank my wife, my daughter, family and friends.

I am so thankful that I have you in my life pushing me when I am ready to give up.

I would like to thank the PSUT academic faculty, and sincerely thank my advisor, Dr.

Khaldoon Abugharbieh, for his guidance and support throughout this study, and especially for his confidence in me.

I would like to say thanks to my colleagues at PSUT and my colleagues at work and my friends for their help and technical support.

Among them: Waseem Al-Akal, Abdallah Hasan, Hazem Marar, Tareq Maaita and Mustafa Shihadeh.

I am extending my thanks to the examiners Prof.

Mohammad Mismar, Dr.

Fadi Shahroury, and Dr.

Bassam Jamil for their valuable discussions and advices.

Finally, my thanks go to all the people who supported me to complete this study directly or indirectly.

التخصصات الرئيسية

الهندسة الكهربائية

الموضوعات

عدد الصفحات

110

قائمة المحتويات

Table of contents.

Abstract.

Abstract in Arabic.

Chapter One : Introduction.

Chapter Two : Literature review.

Chapter Three : Methodology.

Chapter Four : The proposed flip-flop circuit.

Chapter Five : Conclusion and future work.

References.

نمط استشهاد جمعية علماء النفس الأمريكية (APA)

Bundug, Usamah Nasir. (2017). A D-type flip-flop with enhanced timing using CMOS technology and low supply voltage. (Master's theses Theses and Dissertations Master). Princess Sumaya University for Technology, Jordan
https://search.emarefa.net/detail/BIM-743830

نمط استشهاد الجمعية الأمريكية للغات الحديثة (MLA)

Bundug, Usamah Nasir. A D-type flip-flop with enhanced timing using CMOS technology and low supply voltage. (Master's theses Theses and Dissertations Master). Princess Sumaya University for Technology. (2017).
https://search.emarefa.net/detail/BIM-743830

نمط استشهاد الجمعية الطبية الأمريكية (AMA)

Bundug, Usamah Nasir. (2017). A D-type flip-flop with enhanced timing using CMOS technology and low supply voltage. (Master's theses Theses and Dissertations Master). Princess Sumaya University for Technology, Jordan
https://search.emarefa.net/detail/BIM-743830

لغة النص

الإنجليزية

نوع البيانات

رسائل جامعية

رقم السجل

BIM-743830