VHDL and FPGA implementation of max membership principle based on defuzzifier unit

الملخص EN

the fuzzy data that obtained from the fuzzification process is not appropriate for the real time applications and have to be converted into crisp form.

The conversion of data from fuzzy form to crisp form is known as the defuzzification, also called as "rounding off".

This paper proposes VLSI architecture of a Max Membership Principle (MMP) defuzzification method.

The MMP of defuzzification is simple and is being generally used in comparison to more complex weighted average defuzzification method.

The proposed architecture has been modeled in VHDL and implemented in XILINX and Spartan - 3 field programmable gate arrays (FPGA).

It is more efficient in the area and the speed of operation in comparison to a more complex architecture used for the weighted average method.

The functional analysis has revealed that the proposed architecture is implementing MMP based defuzzifier efficiently and accurately.