Vertical shuffle scheduling-based decoder for joint MIMO detection and channel decoding

الملخص EN

This paper presents a novel architecture of a soft Non-Binary Low Density Parity Check (NB-LDPC) decoder for joint iterative Multiple-Input Multiple-Output (MIMO) receivers.

The proposed architecture implements a single variable node processor where the Log Likelihood Ratio (LLR) computation block is removed.

It also implements a single Check Node (CN) processor that is composed of six Elementary Check Nodes.

The architecture is able to decode the rate R=1/2 with frame length N= 384Low Density Parity Check (LDPC) code using a 64 QAM modulation.

To our knowledge, it is the first soft decoder architecture that implements the belief propagation algorithm based on vertical shuffle schedule.

Synthesis results show that the proposed architecture consumes 6.476 K slices and runs at a maximum clock frequency of 70 MHz.

Taking only the decoding process part alone, 188 clock cycles are required to perform decoding iterations.