Design and implementation of gray scale JPEG CODEC on spartan-3E

الملخص EN

This paper presents the design and implementation of the hardware JPEG CODEC for gray scale images.

The architecture is designed in a way based on modules, all modules are sharing between JPEG encoder and decoder circuit .

Each module was designed to implement forward and backward function and they have separate control signals.

The JPEG CODEC (Compressor, Decompressor) architecture achieves high throughput with a deep and optimized pipeline, with a target to FPGA device implementation.

The designed architectures are detailed in this paper and they were described in VHDL, simulated and physically mapped to XC3S500 FPGAs.

The JPEG CODEC pipeline has a minimum latency of 166 clock cycles, given the full modular pipeline depth.

The CODEC can process a 512X 512 pixels still image in 5.2ms, reaching a maximum processing rate of 190 frames per second.