Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis
Joint Authors
Srikanthan, Thambipillai
Sinha, Sharad
Source
International Journal of Reconfigurable Computing
Issue
Vol. 2014, Issue 2014 (31 Dec. 2014), pp.1-14, 14 p.
Publisher
Hindawi Publishing Corporation
Publication Date
2014-10-21
Country of Publication
Egypt
No. of Pages
14
Main Subjects
Information Technology and Computer Science
Abstract EN
Multiplication is a common operation in many applications and there exist various types of multiplication operations.
Current high level synthesis (HLS) flows generally treat all multiplication operations equally and indistinguishable from each other leading to inefficient mapping to resources.
This paper proposes algorithms for automatically identifying the different types of multiplication operations and investigates the ensemble of these different types of multiplication operations.
This distinguishes it from previous works where mapping strategies for an individual type of multiplication operation have been investigated and the type of multiplication operation is assumed to be known a priori.
A new cost model, independent of device and synthesis tools, for establishing priority among different types of multiplication operations for mapping to on-chip DSP blocks is also proposed.
This cost model is used by a proposed analysis and priority ordering based mapping strategy targeted at making efficient use of hard DSP blocks on FPGAs while maximizing the operating frequency of designs.
Results show that the proposed methodology could result in designs which were at least 2× faster in performance than those generated by commercial HLS tool: Vivado-HLS.
American Psychological Association (APA)
Sinha, Sharad& Srikanthan, Thambipillai. 2014. Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis. International Journal of Reconfigurable Computing،Vol. 2014, no. 2014, pp.1-14.
https://search.emarefa.net/detail/BIM-1037617
Modern Language Association (MLA)
Sinha, Sharad& Srikanthan, Thambipillai. Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis. International Journal of Reconfigurable Computing No. 2014 (2014), pp.1-14.
https://search.emarefa.net/detail/BIM-1037617
American Medical Association (AMA)
Sinha, Sharad& Srikanthan, Thambipillai. Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis. International Journal of Reconfigurable Computing. 2014. Vol. 2014, no. 2014, pp.1-14.
https://search.emarefa.net/detail/BIM-1037617
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-1037617