A Low Leakage Autonomous Data Retention Flip-Flop with Power Gating Technique

Abstract EN

With the scaling of technology process, leakage power becomes an increasing portion of total power.

Power gating technology is an effective method to suppress the leakage power in VLSI design.

When the power gating technique is applied in sequential circuits, such as flip-flops and latches, the data retention is necessary to store the circuit states.

A low leakage autonomous data retention flip-flop (ADR-FF) is proposed in this paper.

Two high- V t h transistors are utilized to reduce the leakage power consumption in the sleep mode.

The data retention cell is composed of a pair of always powered cross-coupled inverters in the slave latch.

No extra control signals and complex operations are needed for controlling the data retention and restoration.

The data retention flip-flops are simulated with NCSU 45 nm technology.

The postlayout simulation results show that the leakage power of the ADR-FF reduces 51.39% compared with the Mutoh-FF.

The active power of the ADR-FF is almost equal to other data retention flip-flops.

The average state mode transition time of ADR-FF decreases 55.98%, 51.35%, and 21.07% as compared with Mutoh-FF, Balloon-FF, and Memory-TG-FF, respectively.

Furthermore, the area overhead of ADR-FF is smaller than other data retention flip-flops.