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Asynchronous Advanced Encryption Standard Hardware with Random Noise Injection for Improved Side-Channel Attack Resistance
Joint Authors
Kim, Yong-Bin
Kotipalli, Siva
Choi, Minsu
Source
Journal of Electrical and Computer Engineering
Issue
Vol. 2014, Issue 2014 (31 Dec. 2014), pp.1-13, 13 p.
Publisher
Hindawi Publishing Corporation
Publication Date
2014-07-20
Country of Publication
Egypt
No. of Pages
13
Main Subjects
Information Technology and Computer Science
Abstract EN
This work presents the design, hardware implementation, and performance analysis of novel asynchronous AES (advanced encryption standard) Key Expander and Round Function, which offer increased side-channel attack(SCA) resistance.
These designs are based on a delay-insensitive (DI) logic paradigm known as null convention logic (NCL), which supports useful properties for resisting SCAs including dual-rail encoding, clock-free operation, and monotonic transitions.
Potential benefits include reduced and more uniform switching activities and reduced signal-to-noise (SNR) ratio.
A novel method to further augment NCL AES hardware with random voltage scaling technique is also presented for additional security.
Thereby, the proposed components leak significantly less side-channel information than conventional clocked approaches.
To quantitatively verify such improvements, functional verification and WASSO (weighted average simultaneous switching output) analysis have been carried out on both conventional synchronous approach and the proposed NCL based approach using Mentor Graphics ModelSim and Xilinx simulation tools.
Hardware implementation has been carried out on both designs exploiting a specified side-channel attack standard evaluation FPGA board, called SASEBO-GII, and the corresponding power waveforms for both designs have been collected.
Along with the results of software simulations, we have analyzed the collected waveforms to validate the claims related to benefits of the proposed cryptohardware design approach.
American Psychological Association (APA)
Kotipalli, Siva& Kim, Yong-Bin& Choi, Minsu. 2014. Asynchronous Advanced Encryption Standard Hardware with Random Noise Injection for Improved Side-Channel Attack Resistance. Journal of Electrical and Computer Engineering،Vol. 2014, no. 2014, pp.1-13.
https://search.emarefa.net/detail/BIM-1040532
Modern Language Association (MLA)
Kotipalli, Siva…[et al.]. Asynchronous Advanced Encryption Standard Hardware with Random Noise Injection for Improved Side-Channel Attack Resistance. Journal of Electrical and Computer Engineering No. 2014 (2014), pp.1-13.
https://search.emarefa.net/detail/BIM-1040532
American Medical Association (AMA)
Kotipalli, Siva& Kim, Yong-Bin& Choi, Minsu. Asynchronous Advanced Encryption Standard Hardware with Random Noise Injection for Improved Side-Channel Attack Resistance. Journal of Electrical and Computer Engineering. 2014. Vol. 2014, no. 2014, pp.1-13.
https://search.emarefa.net/detail/BIM-1040532
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-1040532