Optimization of Lookup Schemes for Flow-Based Packet Classification on FPGAs

Abstract EN

Packet classification has become a key processingfunction to enable future flow-based networking schemes.

Asnetwork capacity increases and new services are deployed, bothhigh throughput and reconfigurability are required forpacket classification architectures.

FPGA technology can providethe best trade-off among them.

However, to date, lookupstages have been mostly developed as independent schemesfrom the classification stage, which makes their efficient integration on FPGAs difficult.

In this context, we propose a newinterpretation of the lookup problem in the general context ofpacket classification, which enables comparing existing lookupschemes on a common basis.

From this analysis, we recognizenew opportunities for optimization of lookup schemes and theirassociated classification schemes on FPGA.

In particular, wefocus on the most appropriate candidate for future networkingneeds and propose optimizations for it.

To validate our analysis,we provide estimation and implementation results for typicallookup architectures on FPGA and observe their conveniencefor different lookup and classification cases, demonstrating thebenefits of our proposed optimization.