Using Genetic Algorithms for Hardware Core Placement and Mapping in NoC-Based Reconfigurable Systems

Abstract EN

Mapping of cores has been an important activityin NoC-based system design aimed to find the best topologicallocation onto the NoC, such that the metrics of interest canbe greatly optimized.

In the last years, partial reconfigurablesystems (PRSs) have included Networks-on-Chips (NoCs) as theircommunication structure, adding complexity to the problem ofmapping.

Several works have proposed specific and robust NoCarchitectures for PRSs, forming indirect and irregular networks,in which cases the mapping and placement problems mustbe treated altogether.

The placement deals with the physicalpositioning of those cores inside the reconfigurable device.

Upto now, to the best of our knowledge, the mapping-placementproblem for those kinds of architectures has not been addressedyet.

In this work, the problem formalization for the design-timehardware core placement and mapping in PRS-NoCs is proposedand methodologies for solving it with genetic algorithms (GAs)are presented.

Several GA crossovers and methodologies are comparedfor obtaining the best solution.

Results have shown that bestGA solution obtained, in average, communication costs with 4%of penalty when compared with global minimum cost, obtained ina semiexhaustive approach.

In addition, the algorithm presentslow execution times.