Applying Partial Power-Gating to Direction-Sliced Network-on-Chip

Abstract EN

Network-on-Chip (NoC) is one of critical communication architectures for future many-core systems.

As technology is continually scaling down, on-chip network meets the increasing leakage power crisis.

As a leakage power mitigation technique, power-gating can be utilized in on-chip network to solve the crisis.

However, the network performance is severely affected by the disconnection in the conventional power-gated NoC.

In this paper, we propose a novel partial power-gating approach to improve the performance in the power-gated NoC.

The approach mainly involves a direction-slicing scheme, an improved routing algorithm, and a deadlock recovery mechanism.

In the synthetic traffic simulation, the proposed design shows favorable power-efficiency at low-load range and achieves better performance than the conventional power-gated one.

For the application trace simulation, the design in the mesh/torus network consumes 15.2%/18.9% more power on average, whereas it can averagely obtain 45.0%/28.7% performance improvement compared with the conventional power-gated design.

On balance, the proposed design with partial power-gating has a better tradeoff between performance and power-efficiency.