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Global Scheduling Heuristics for Multicore Architecture
Joint Authors
Kiran, D. C.
Gurunarayanan, S.
Misra, Janardan Prasad
Nawal, Abhijeet
Source
Issue
Vol. 2015, Issue 2015 (31 Dec. 2015), pp.1-12, 12 p.
Publisher
Hindawi Publishing Corporation
Publication Date
2015-06-02
Country of Publication
Egypt
No. of Pages
12
Main Subjects
Abstract EN
This work discusses various compiler level global scheduling techniques for multicore processors.
The main contribution of the work is to delegate the job of exploiting fine grained parallelism to the compiler, thereby reducing the hardware overhead and the programming complexity.
This goal is achieved by decomposing a sequential program into multiple subblocks and constructing subblock dependency graph (SDG).
The proposed schedulers select subblocks from the SDG and schedules it on different cores, by ensuring the correct order of execution of subblocks.
In conjunction with parallelization techniques, locality optimizations are performed to minimize communication overhead between the cores.
The results observed are indicative of better and balanced speed-up per watt.
American Psychological Association (APA)
Kiran, D. C.& Gurunarayanan, S.& Misra, Janardan Prasad& Nawal, Abhijeet. 2015. Global Scheduling Heuristics for Multicore Architecture. Scientific Programming،Vol. 2015, no. 2015, pp.1-12.
https://search.emarefa.net/detail/BIM-1076553
Modern Language Association (MLA)
Kiran, D. C.…[et al.]. Global Scheduling Heuristics for Multicore Architecture. Scientific Programming No. 2015 (2015), pp.1-12.
https://search.emarefa.net/detail/BIM-1076553
American Medical Association (AMA)
Kiran, D. C.& Gurunarayanan, S.& Misra, Janardan Prasad& Nawal, Abhijeet. Global Scheduling Heuristics for Multicore Architecture. Scientific Programming. 2015. Vol. 2015, no. 2015, pp.1-12.
https://search.emarefa.net/detail/BIM-1076553
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-1076553