Hybrid Network-on-Chip: An Application-Aware Framework for Big Data

Abstract EN

Burst growing IoT and cloud computing demand exascale computing systems with high performance and low power consumption to process massive amounts of data.

Modern system platforms based on fundamental requirements encounter a performance gap in chasing exponential growth in data speed and amount.

To narrow the gap, a heterogamous design gives us a hint.

A network-on-chip (NoC) introduces a packet-switched fabric for on-chip communication and becomes the de facto many-core interconnection mechanism; it refers to a vital shared resource for multifarious applications which will notably affect system energy efficiency.

Among all the challenges in NoC, unaware application behaviors bring about considerable congestion, which wastes huge amounts of bandwidth and power consumption on the chip.

In this paper, we propose a hybrid NoC framework, combining buffered and bufferless NoCs, to make the NoC framework aware of applications’ performance demands.

An optimized congestion control scheme is also devised to satisfy the requirement in energy efficiency and the fairness of big data applications.

We use a trace-driven simulator to model big data applications.

Compared with the classical buffered NoC, the proposed hybrid NoC is able to significantly improve the performance of mixed applications by 17% on average and 24% at the most, decrease the power consumption by 38%, and improve the fairness by 13.3%.