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A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance
Joint Authors
Wilson, David
Shastri, Aniruddha
Stitt, Greg
Source
International Journal of Reconfigurable Computing
Issue
Vol. 2017, Issue 2017 (31 Dec. 2017), pp.1-17, 17 p.
Publisher
Hindawi Publishing Corporation
Publication Date
2017-08-21
Country of Publication
Egypt
No. of Pages
17
Main Subjects
Information Technology and Computer Science
Abstract EN
Computing systems with field-programmable gate arrays (FPGAs) often achieve fault tolerance in high-energy radiation environments via triple-modular redundancy (TMR) and configuration scrubbing.
Although effective, TMR suffers from a 3x area overhead, which can be prohibitive for many embedded usage scenarios.
Furthermore, this overhead is often worsened because TMR often has to be applied to existing register-transfer-level (RTL) code that designers created without considering the triplicated resource requirements.
Although a designer could redesign the RTL code to reduce resources, modifying RTL schedules and resource allocations is a time-consuming and error-prone process.
In this paper, we present a more transparent high-level synthesis approach that uses scheduling and binding to provide attractive tradeoffs between area, performance, and redundancy, while focusing on FPGA implementation considerations, such as resource realization costs, to produce more efficient architectures.
Compared to TMR applied to existing RTL, our approach shows resource savings up to 80% with average resource savings of 34% and an average clock degradation of 6%.
Compared to the previous approach, our approach shows resource savings up to 74% with average resource savings of 19% and an average heuristic execution time improvement of 96x.
American Psychological Association (APA)
Wilson, David& Shastri, Aniruddha& Stitt, Greg. 2017. A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance. International Journal of Reconfigurable Computing،Vol. 2017, no. 2017, pp.1-17.
https://search.emarefa.net/detail/BIM-1169433
Modern Language Association (MLA)
Wilson, David…[et al.]. A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance. International Journal of Reconfigurable Computing No. 2017 (2017), pp.1-17.
https://search.emarefa.net/detail/BIM-1169433
American Medical Association (AMA)
Wilson, David& Shastri, Aniruddha& Stitt, Greg. A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance. International Journal of Reconfigurable Computing. 2017. Vol. 2017, no. 2017, pp.1-17.
https://search.emarefa.net/detail/BIM-1169433
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-1169433