FPGA Implementation of A∗ Algorithm for Real-Time Path Planning
Joint Authors
Wang, Tianqi
Zhou, Yuzhi
Jin, Xi
Source
International Journal of Reconfigurable Computing
Issue
Vol. 2020, Issue 2020 (31 Dec. 2020), pp.1-11, 11 p.
Publisher
Hindawi Publishing Corporation
Publication Date
2020-08-17
Country of Publication
Egypt
No. of Pages
11
Main Subjects
Information Technology and Computer Science
Abstract EN
The traditional A∗ algorithm is time-consuming due to a large number of iteration operations to calculate the evaluation function and sort the OPEN list.
To achieve real-time path-planning performance, a hardware accelerator’s architecture called A∗ accelerator has been designed and implemented in field programmable gate array (FPGA).
The specially designed 8-port cache and OPEN list array are introduced to tackle the calculation bottleneck.
The system-on-a-chip (SOC) design is implemented in Xilinx Kintex-7 FPGA to evaluate A∗ accelerator.
Experiments show that the hardware accelerator achieves 37–75 times performance enhancement relative to software implementation.
It is suitable for real-time path-planning applications.
American Psychological Association (APA)
Zhou, Yuzhi& Jin, Xi& Wang, Tianqi. 2020. FPGA Implementation of A∗ Algorithm for Real-Time Path Planning. International Journal of Reconfigurable Computing،Vol. 2020, no. 2020, pp.1-11.
https://search.emarefa.net/detail/BIM-1174000
Modern Language Association (MLA)
Zhou, Yuzhi…[et al.]. FPGA Implementation of A∗ Algorithm for Real-Time Path Planning. International Journal of Reconfigurable Computing No. 2020 (2020), pp.1-11.
https://search.emarefa.net/detail/BIM-1174000
American Medical Association (AMA)
Zhou, Yuzhi& Jin, Xi& Wang, Tianqi. FPGA Implementation of A∗ Algorithm for Real-Time Path Planning. International Journal of Reconfigurable Computing. 2020. Vol. 2020, no. 2020, pp.1-11.
https://search.emarefa.net/detail/BIM-1174000
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-1174000