Scalable THz Network-On-Chip Architecture for Multichip Systems

Abstract EN

While THz wireless network-on-chip (WiNoC) introduces considerably high bandwidth, due to the high path loss, it cannot be used for communication between far apart nodes, especially in a multichip architecture.

In this paper, we introduce a cellular and scalable architecture to reuse the frequencies of the chips.

Moreover, we use a novel structure called parallel-plate waveguide (PPW) that is suitable for interchip communication.

The low-loss property of this waveguide lets us increase the number of chips.

Each chip has a wireless node as a gateway for communicating with other chips.

To shorten the length of intra- and interchip THz links, the optimum configuration is determined by leveraging the multiobjective simulating annealing (SA) algorithm.

Finally, we compare the performance of the proposed THz multichip NoC with a conventional millimeter-wave one.

Our simulation results indicate that when the system scales up from four to sixteen chips, the throughput of our design is decreased about 5.8%, while for millimeter-wave NoC, this reduction is about 21%.

Furthermore, the average latency growth of our system is only 1% compared with about 40% increase for the millimeter-wave NoC.