![](/images/graphics-bg.png)
Design and Analysis of Nanoscaled Recessed-SD SOI MOSFET-Based Pseudo-NMOS Inverter for Low-Power Electronics
Joint Authors
Priya, Anjali
Srivastava, Nilesh Anand
Mishra, R. A.
Source
Issue
Vol. 2019, Issue 2019 (31 Dec. 2019), pp.1-12, 12 p.
Publisher
Hindawi Publishing Corporation
Publication Date
2019-03-28
Country of Publication
Egypt
No. of Pages
12
Main Subjects
Abstract EN
In this paper, a comparative analysis of nanoscaled triple metal gate (TMG) recessed-source/drain (Re-S/D) fully depleted silicon-on-insulator (FD SOI) MOSFET has been presented for the design of the pseudo-NMOS inverter in the nanometer regime.
For this, firstly, an analytical modeling of threshold voltage has been proposed in order to investigate the short channel immunity of the studied device and also verified against simulation results.
In this structure, the novel concept of backchannel inversion has been utilized for the study of device performance.
The threshold voltage has been analyzed by varying the parameters of the device like the ratio of metal gate length and the recessed-source/drain thickness for TMG Re-S/D SOI MOSFET.
Drain-induced barrier lowering (DIBL) has also been explored in terms of recessed-source/drain thickness and the metal gate length ratio to examine short channel effects (SCEs).
For the exact estimation of results, the comparison of the existing multimetal gate structures with TMG Re-S/D SOI MOSFET has also been taken under study in terms of electrostatic performance, i.e., threshold voltage, subthreshold slope, and on-off current ratio.
These structures are investigated with the TCAD numerical simulator from Silvaco ATLAS.
Furthermore, for the first time, TMG Re-S/D FD SOI MOSFET-based pseudo-NMOS inverter has been designed to observe the device performance at circuit levels.
It has been found that the device offers high noise immunity with optimum switching characteristics, and the propagation delay of the studied circuit is recorded as 0.43 ps.
American Psychological Association (APA)
Priya, Anjali& Srivastava, Nilesh Anand& Mishra, R. A.. 2019. Design and Analysis of Nanoscaled Recessed-SD SOI MOSFET-Based Pseudo-NMOS Inverter for Low-Power Electronics. Journal of Nanotechnology،Vol. 2019, no. 2019, pp.1-12.
https://search.emarefa.net/detail/BIM-1183752
Modern Language Association (MLA)
Priya, Anjali…[et al.]. Design and Analysis of Nanoscaled Recessed-SD SOI MOSFET-Based Pseudo-NMOS Inverter for Low-Power Electronics. Journal of Nanotechnology No. 2019 (2019), pp.1-12.
https://search.emarefa.net/detail/BIM-1183752
American Medical Association (AMA)
Priya, Anjali& Srivastava, Nilesh Anand& Mishra, R. A.. Design and Analysis of Nanoscaled Recessed-SD SOI MOSFET-Based Pseudo-NMOS Inverter for Low-Power Electronics. Journal of Nanotechnology. 2019. Vol. 2019, no. 2019, pp.1-12.
https://search.emarefa.net/detail/BIM-1183752
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-1183752