Power optimization of binary multiplier based on FPGA

Abstract EN

In the VLSI circuits, power dissipation is a critical design parameter and it plays a vital role in the performance of different digital systems.

The decrease in chip size along with the increase in chip density and complexity will increase the difficulty in designing higher performance and low power digital systems.

Therefore, achieving a fast and low power system is the major concern of VLSI designers.

Most of the digital systems have different math operations in their architectures.

This paper focuses on the multiplication operation.

Multiplication requires more iterations, long time, large area, and consumes high power of the digital system compared with the other basic computation operations.

Hence to improve the system's performance, it is required to design a high speed and low power multiplier.

In this paper, a dynamic power dissipation is targeted; therefore, different designs of multiplier algorithms such as a sequential multiplier, array multiplier, Booth's multiplier (Radix-2), and modified Booth's multiplier (Radix-4) are proposed to investigate the design that consumes the lowest dynamic power.

New techniques such as VHDL and Basic Logic Elements are presented and applied to the proposed designs.

The VHDL approach satisfies the highest optimization criteria in dynamic power at 87% for the sequential multiplier than the traditional ones.