Dynamic power consumption in CMOS n bit full-adder circuit

Joint Authors

Hasan, Amal F.
Hasan, Qusayy H.

Source

Engineering and Technology Journal

Issue

Vol. 39, Issue 5A (31 May. 2021), pp.754-767, 14 p.

Publisher

University of Technology

Publication Date

2021-05-31

Country of Publication

Iraq

No. of Pages

14

Main Subjects

Electronic engineering

Topics

Abstract EN

This paper discusses power consumption in the full adder circuit using some fabrication technologies.

Though many studies related to power consumption in the full adder circuit were performed, however, few investigations about the effect of the number of bits on the power consumption are addressed.

In this paper, the effect of changing the number of bits on the power consumption and time delay of the full adder circuit will be observed and the effect of changing the technology size is going to be calculated.

The results will show that there is a direct relationship between the number of bits and power

American Psychological Association (APA)

Hasan, Amal F.& Hasan, Qusayy H.. 2021. Dynamic power consumption in CMOS n bit full-adder circuit. Engineering and Technology Journal،Vol. 39, no. 5A, pp.754-767.
https://search.emarefa.net/detail/BIM-1282600

Modern Language Association (MLA)

Hasan, Amal F.& Hasan, Qusayy H.. Dynamic power consumption in CMOS n bit full-adder circuit. Engineering and Technology Journal Vol. 39, no. 5A (2021), pp.754-767.
https://search.emarefa.net/detail/BIM-1282600

American Medical Association (AMA)

Hasan, Amal F.& Hasan, Qusayy H.. Dynamic power consumption in CMOS n bit full-adder circuit. Engineering and Technology Journal. 2021. Vol. 39, no. 5A, pp.754-767.
https://search.emarefa.net/detail/BIM-1282600

Data Type

Journal Articles

Language

English

Notes

Includes bibliographical references : p. 765-766

Record ID

BIM-1282600