Design of Area Efficient, Low-Power and Reliable Transmission Gate-based 10T SRAM Cell for Biomedical Application

Abstract EN

There is an immense necessity of several kilo bytes(kb) of embedded memory for Biomedical systems which typically operate in the sub-threshold domain with perfect efficiency.

SRAM (Static Random Access Memory) dominates the total power consumption and the overall silicon area, as 70% of the die has been occupied by them.

This paper proposes the design of a transmission gate-based SRAM cell for biomedical application eliminating the use of peripheral circuitry during the read operation.

It commences the read operation directly with the help of transmission gates with which the data stored in the storage nodes can be read, instead of using the precharge and sense amplifier circuits which suits better for the implantable devices.

This topology offers smaller area, reduced delay, low power consumption, and improved data stabilization in the read operation.

The cell is implemented in 45nm CMOS technology operated at 0.45v.