Usability analysis of on-chip inductive coupling management and reduction techniques

Abstract EN

As very large scale integration (VLSI) technology progresses toward the nanometer range and the operating frequency moves higher into the gigahertz range, parasitic on-chip inductance has become a major concern both from the functionality and performance points of view.

The effects of on-chip inductance are strongly associated with higher frequency signal content, denser geometries, and reductions of both resistance and capacitance by copper interconnect and low-K devices.

All of these are considered amongst the key practices currently being utilized by designers of state-of-the-art chips to raise the performance levels.

A solution to completely address the issue of inductive coupling has not been identified yet.

Several point solutions have been proposed to address particular situations.

This paper surveys these proposed solutions and discusses their effectiveness in combating the problem.

At the end, the paper will present recommendations about the best techniques to be used under given circumstances and the required conditions for the highest benefit from each technique.