Implementation of root finding algorithm of minimum phase filter using vhdl

Abstract EN

Root-finding is an oldest classical problem, which is still an important research topic, due to its impact on computational algebra and geometry.

In communications systems, when the impulse response of the channel is minimum phase the state of equalization algorithm is reduced and the spectral efficiency will improved.

To make the channel impulse response minimum phase the profiler which is called minimum phase filter is used, the adaptation of the minimum phase filter need root finding algorithm.

In this paper, the VHDL implementation of the root finding algorithm introduced by Clark and Hau is introduced.

VHDL program is used in the work, to find the roots of two channels and make them minimum phase, the obtained output results are similar in accuracy to the past work results, which is built by using MATLAB program.

Using VHDL is necessary in FPGAs for building hardware of the root finding algorithm in lower cost and time.

MATLAB program is used only for displaying the input and output discrete signals of tested channels.