An FPGA based a digital circuit design for route optimization

Abstract EN

Route optimization is searching problem to find the shortest path from starting to end point within certain criteria.

In this paper, a digital circuit design implementation was presented according to the Dijkstra algorithms and with new digital technology.

The proposed circuit is built using VHDL and simulated using Xilinx ISE 9.2i package.

The test of the implemented circuit was made by use a 25 point network map to select the shortest path between any two specific points (from point 3 to point 24).

Simulation behavioral model results show that proposed circuit satisfies the specified operational requirements.

The result appears this requirement with a short time (depend on the clock frequency used 50MHz).

Furthermore, this circuit is flexible to increase the number of point in the map network.