Neuro-swarm intelligence for digital circuits design and simulation based on FPGA

Dissertant

Mahdi, Firas Rasul

Thesis advisor

Akkar, Hanan Abd al-Rida

University

University of Technology

Faculty

-

Department

Department of Electrical Engineering

University Country

Iraq

Degree

Master

Degree Date

2010

English Abstract

Swarm Intelligence (SI) is based on collective behavior of self organized group of particles.

Each particle is following a relatively simple set of rules and interacting with only its neighbor surrounding particles.

Flocking behavior is when a swarm is acting similarly to group of birds.

Particle Swarm Optimization (PSO) has been an increasingly interesting topic in the field of computational intelligence.

PSO is another optimization algorithm that falls under the soft computing address.

As such it, lends itself as being applicable to a wide variety of optimization problem.

One application of PSO that has tremendous success is in the field of Artificial Neural Networks (ANNs) training.

In this thesis the adaption of the ANN weights using PSO was proposed as a mechanism to improve the performance of ANN.

In which each particle in the swarm has been proposed as a set of weights needed for training each Neural Network (NN) to obtain the same target results and obtain zero error value.

For this purpose we modified the MATLAB PSO toolbox to be suitable for the taken application (implementation of ANN digital circuits), the modification was in the environment of the search space which mean instead of searching all the real values in the search space, the search will be in the integer values of the search space only.

One of the major constraints on the hardware implementations of ANNs is the amount of circuitry required to perform the multiplication of each input by its corresponding weight and there subsequent addition.

This thesis confines the multiplication digital circuits to only AND gates utilized from PSO advantages especially its free derivative transfer function.

Field Programmable Gate Array (FPGA) is a suitable hardware for NN design and simulation as it preserves the parallel architecture of the neurons in a layer and offers flexibility in reconfiguration and cost issues.

FPGAs are becoming a critical part of every system design.

Many vendors offer many different architectures and processes for the FPGA.

In this thesis Xilinx Integrated Synthesis Environment (ISE) 3.1i foundation series has been used with schematic entry design tools for the purpose of design and simulation of the intended NNs.

For the proposed design training is done off chip, in this way less hardware is required.

As the training process occur only once in the life time of an application, this method does not reduce the ANN functionality.

This thesis introduces two ANN digital circuits: full adder logic circuit and four bit Arithmetic Logic Unit (ALU).

Main Subjects

Information Technology and Computer Science

Topics

• Digital electronics

• APA
• MLA
• AMA

Language

English

Data Type

Arab Theses

Record ID

BIM-305264