A second-order single loop oversampling analog-to digital converter (ADC)‎ with proposed hybrid feed forwardfeedback architecture

Abstract EN

This paper proposes hy brid architecture of feedforward/fee dbac k second order single-loop modulator for high resolution analog-to-digital converter (ADC) applications.

Differe nt techniques for ove rsampling modulator are discussed.

The proposed architecture consists of three stages.

The first stage is nd 2 order single loop oversampling ADC with novel fe edforward/feedback architecture.

In the second stage, an error cancellation circ uit (ECC) is proposed at the output of the modulator to noise shaping of quantization noise.

In addition, the third stage isa decimation filter in order to reduce the oversampling ratio (OSR) which is suitable for broadband applications.

With low OSR=24, the signal-to-noise ratio (SNR) is improved about 55 dB if c ompared with traditional arc hite cture (feedback singleloop high order topology ).

The achieved resolution or the effective numbe r of bits (ENOB) is (22-bit).

With high OSR=256, the net improveme nt in quantization noise reduc tion is 64 dB if compared with feedforward architecture (single-loop high order) and the ENOB=28.

Finally a 1-bit quantizer is used in the proposed architecture which greatly dec reases the circ uit implementation c omplexity and powe r consumption.

Simulation results show the superiority performance of proposed hy brid architecture as compared with traditional modulator topologies (feedforward and feedback).