FPGA versus ASIC implementation of radix-8 scalable montgomery modular multiplier

Abstract EN

Traditional ASIC implementations have the well-known draw-back of reduced flexibility compared to software implementations.

Since modern security protocols are increasingly defined to be algorithm independent, a high degree of flexibility with respect to the cryptographic algorithms is desirable.

A promising solution which combines high flexibility with the speed and physical security of traditional hardware is the implementation of cryptographic algorithms on reconfigurable devices such as FPGA.

In this paper we compare–in terms of area and speed- FPGA implementation of radix scalable Montgomery modular multiplier using retiming technique with ASIC implementation for different word sizes of operands.

The simulation data were generated using Mentor Graphics CAD tools.