A pipelined fault tolerant architecture for real time DSP applications
Other Title(s)
معمارية الخط الإنتاجي متسامحة الأخطاء لتطبيقات معالجة الإشارة الرقمية
Author
Source
al-Rafidain Engineering Journal
Issue
Vol. 16, Issue 4 (31 Oct. 2008)16 p.
Publisher
University of Mosul College of Engineering
Publication Date
2008-10-31
Country of Publication
Iraq
No. of Pages
16
Main Subjects
Topics
Abstract EN
This paper presents a new, expandable, pipelined linear array architecture designed for transparently tolerating processor failures for real-time DSP applications.
The proposed system use twelve TMS320C40 DSP processors ( Processor Modules PMs ) to construct ten stages pipelined system with two spare processors (SPs).
However, the system can be expanded to increase the pipeline stages and the performance, and adding more spare processors to increase the dependability and reliability of the system.
In Proposed scheme, the system can automatically reconfigure itself in the event of failure in one or two of its DSP processors and the computations continue unhindered without noticeable performance degradation.
Each DSP processor communicates with neighboring processors through a high speed communication ports ( commport ).
Some of these commports in every processor are used as a bypass links in case of failure of one or two processors.
The system uses the forward-task-shift (FTS) mechanism to tolerate the fault by assigning the function of the failed processor to the next fault-free processor.
American Psychological Association (APA)
Mahmud, Ahmad Falih. 2008. A pipelined fault tolerant architecture for real time DSP applications. al-Rafidain Engineering Journal،Vol. 16, no. 4.
https://search.emarefa.net/detail/BIM-338097
Modern Language Association (MLA)
Mahmud, Ahmad Falih. A pipelined fault tolerant architecture for real time DSP applications. al-Rafidain Engineering Journal Vol. 16, no. 4 (2008).
https://search.emarefa.net/detail/BIM-338097
American Medical Association (AMA)
Mahmud, Ahmad Falih. A pipelined fault tolerant architecture for real time DSP applications. al-Rafidain Engineering Journal. 2008. Vol. 16, no. 4.
https://search.emarefa.net/detail/BIM-338097
Data Type
Journal Articles
Language
English
Notes
Includes bibliographical references
Record ID
BIM-338097