Design guidelines for high-speed two-stage cmos operational amplifiers

Abstract EN

This paper presents a well-defined procedure for the design of high-speed twostage CMOS operational amplifiers.

Cascode-compensated amplifiers with good trade-offs between speed, power and stability that make them suitable for high-speed applications are discussed.

The structures are analyzed to obtain the required circuitlevel parameters according to particular bandwidth and stability.

A new technique to take into account the effect of transfer function zeros, which are traditionally neglected, is proposed.

The effect of new capacitor sizing rules to split the compensation capacitance and increase the amplifier's speed has also been considered.

Based on these novelties, a new methodology for the design of highspeed operational amplifiers is proposed.