Design and FPGA implementation of two-dimensional discrete wavelet transform architectures using raster-scan method

Abstract EN

In this paper, an FPGA implementation of a 2-dimenional discrete wavelet transform (2-D DWT) is proposed to efficiently construct the corresponding twodimensional architecture by using the raster-scan image method for any given hardware architecture of one dimensional (1-D) wavelet transform filter.

The proposed method is based on lifting scheme architecture.

The resulting architectures are simple, modular and regular for computation of one or multilevel 2-D DWT.

These architectures perform both low pass and high pass filter with multiplierless coefficients calculation.

In addition they require a small on-chip area to download the architectures on FPGA Board (Spartan-3E).

The proposed 2-D architecture consists of: external memory, Row 1-D arithmetic module, column 1-D arithmetic module and internal memory unit.

The row and column 1-D arithmetic units are designed utilizing Biorthogonal filters (5 / 3 and 9 / 7).