Generation and validation of detailed architectures from behavioral VHDL descriptions

Abstract EN

High-level synthesis descriptions allow the specification of complex designs.

With high-level descriptions, hardware-related issues such as synchronization information need not be explicitly included.

Therefore, they must be added to the output of the high-level synthesis tool.

In this paper, we present a Programmable Architecture Translator (PAT) that adds synchronization signals to an RTL description generated by the high-level synthesis tool, AMICAL.

PAT allows the designer to add customized synchronization schemes to the generated architecture and the translation of the entire description into VHDL acceptable by existing logic level synthesis tools.