Automated VHDL composition from AHPL

Abstract EN

Hardware description languages (HDLs) have been widely used for documentation, communication, and verification.

They have also been used as input specification languages to Design Automation (DA) systems which synthesize VLSI layouts.

AHPL is an HDL that has been in use for the past two decades in modeling digital systems.

Recently a language called VHDL (VHSIC Hardware Description Language) developed under the auspices of the United States Department of Defense Very High Speed Integrated Circuits Program, is rapidly emerging as the next generation Design Automation Language.

In this paper, we present a tool for the automatic composition of VHDL descriptions from their equivalent AHPL specifications.

Central to the composition algorithm is a template which is the skeleton of a generic VHDL model consisting of a small subset of VHDL constructs that are sufficient to capture VHDL equivalent descriptions of any input AHPL model.

The Composer will be illustrated with the help of an example.