Counter based response compression for self-testing of PCB interconnections using boundary scan

Abstract EN

This paper presents a counter based response compression technique for selftesting of printed circuit board (PCB) interconnection faults using boundary scan (BS) technique.

It applies walking one/zero test vectors to test interconnection faults.

The implementation requires some modifications to the IEEE Std.

1149.1 BS cells.Three additional MOS transistors are incorporated with the input BS cell, two of them are used as transistor switches to detect fault effect and one is used to latch response data.

A dynamic NOR gate and a dynamic AND gate are constructed with the transistor switches.

Outputs of these NOR and AND gates are connected to a binary counter enable input through a two input multiplexer.

Presence of faults are detected at NOR and AND gate inputs (i.e., transistor switches) and the number of faults are counted by the counter.

The output BS cells are modified to have data enable capability.

This technique is applicable strictly to BS environment.