Partial scan design based on simulated annealing for hard-to-detect faults

Abstract EN

In this paper, we describe algorithms based on Simulated Annealing for selecting a subset of flip-flops to be connected into a scan path.

The objective for selection is to maximize the coverage of faults that are aborted by a sequential fault simulator.

We pose the problem as a combinatorial optimization, and present a heuristic algorithm based on Simulated Annealing.

The SCOAP testability measure is employed to assess the selection of flip-flops during the course of optimization.

Our algorithms form a part of an integrated design package, TOPS, which has been designed as an enhancement to the OASIS standard-cell design automation system available from MCNC [1].

We discuss the TOPS package and its performance on a number of ISCAS’89 benchmarks.

We also present a comparative evaluation of the circuit benchmarks.